1. Field of the Invention
This invention relates to semiconductor apparatus capable of multiple stable electronic states allowing higher order mathematical radix analysis of analog and digital signals. In particular the invention relates to semiconductor apparatus and devices for analog-to-digital conversion and waveform differentiation or integration of electronic signals by use of higher order number systems. The invention discloses construction of semiconductor charge coupled devices for accomplishing the same. In addition the invention relates to novel construction of charge-coupled devices finding applications in electronics, especially with respect to detection and manipulation of electronic signals for A/D conversion, mathematical differentiation, and integration of electronic waveform signals. The device accomplishes direct A/D signal conversion with increased circuit speed while decreasing electronic component density compared to computational circuits based on binary conversion.
2. Description of the Prior Art
In telecommunications and computer processing, digital signals are generally in the form of binary numbers because of two main reasons. First, conventional electronic switching components are in one of two states, namely `OFF` or `ON`. An electronic switch turned ON corresponds to the digit `1` and the same switch turned OFF corresponds to the digit `0`. From an electronic device standpoint the two electronic states, ON/OFF, has been easier to achieve than finding an electronic component that exhibits multiple stable states. Especially it has been found extremely difficult to find electronic components having incremental multiple stable states. The second reason digital circuits are designed with binary numbers is because of signal transmission reliability. Because of noise in signal transmission lines it has been found easier to recognize a `0` and a `1` among random electronic transmission noise than to identify multiple signal strengths among all this noise. This Von Neumann architecture has certainly well served Americas vast computing and digital transmission requirements to this point.
In U.S. Pat. No. 3,958,210, issued to P. A. Levine on May 18, 1976, an electronic system for analog-to-digital conversion was disclosed including a semiconductor charge coupled device, utilizing the properties of semiconductor surface potential wells for charge storage and transfer in response to voltages applied to electrodes overlying the wells. However, the semiconductor charge coupled device portion of that system produced only a digital counting representation (unitary based number system) of the input analog signal, and the system required complex logic circuitry to convert this digital counting representation into the ultimately desired representation in the binary number system. In other words, an analog input representing the number n was converted by the charge coupled device portion into a "unitary" sequence purely of n "ones" (1,1,1, . . . 1,1,1)according to the unitary number system, rather than directly into the desired binary sequence of "ones" and "zeros" according to the binary number system. Complex logic circuitry was thus required for subsequent conversion of the "unitary" sequence into a corresponding binary digital sequence such as (1,0,1 . . . 0,1, 1) representing n=I.times.21 . . . +O.times.2i-I+1.times.2i-2+ . . . +0.times.2,4+I.times.21I.times.20, where i is selected such that I.times.V is the "most significant bit" in the number n.
Need for Higher Radix System
There are a number of reasons to consider a higher order number radix than binary for computing and telecommunication architecture. First of all, analog and digital integrated circuit manufacturing complexity seems to be approaching an optical resolution limit whereby it is becoming difficult to increase the number of gates on a chip. Second, fiber optic transmission lines have greatly allowed cleanup of noise in transmission systems. A major consideration is that while the electronic world is mostly digital the real world is almost entirely analog. And, of course, if the computer world works in binary arithmetic the real world is conventionally a decimal world. The technical disadvantages of binary-based integrated circuit technology are (1) maximum MOST gate complexity of any number system, (2) slowest speed of any radix system, and (3) decreased manufacturing yield because of the huge number of MOSTs required for number representation. It would be extremely desirable to have available an electronic device of more than two stable electronic states because the number of digits, or `gates` required in a computer chip for number representation is a consequence of the mathematical number radix. A higher order digital number radix than binary, as a consequence of requiring far fewer `gates` for number representation, allows much increased circuit speed. This is a consequence of inherent signal delay times, each gate. Decreasing the number of gates would allow much increased circuit speed. Consequent decreased circuit density allows increased manufacturing yield for a given function representation.
Pressures, temperatures, speeds, fluid flows, etc. all change continuously. To deal with this real world analog information typically an electronic circuit converts the signal information from analog to binary digital, then sends the digitized information over a signal transmission system, and then reconverts the binary digital form back to analog. One or more chips are used for analog-to-digital conversion, one or more chips for binary signal transmission, one or more for program storage, one or more for scratch pad read/write, and one or more chips are required for input/output lines, until finally the signal is reconverted from digital-to-analog. These conversion processes require many extremely complicated electronic integrated circuits whereby the total binary conversion times, plus delay due to the huge number of binary switching components results in considerable reduction of circuit speed. Moreover, even faster speeds are required of the Internet, especially for video signal transmission and compression, requiring much faster D-to-A and A-to-D conversion times. Faster electronic circuits for such wave signal processes as integration, differentiation, and multiplexing are desired. A number system analysis shows why a radix higher than binary is desirable.
Number System Considerations
Every positive integer `a` can be expressed in the base system form, EQU a=r.sub.m b.sup.m +r.sub.m-1 b.sup.m-1 + . . . +r.sub.1 b+r.sub.0,
where m is a nonnegative integer and the r's are integers such that, EQU 0.ltoreq.r.sub.m, b and 0.ltoreq.r.sub.i &lt;b for i=0,1, . . . , m-1.
Base number b can be ally positive integer b&gt;1. The number of terms, or digits, in the series representing a numeral decreases greatly as b increases. Comparing, for example, the decimal system to the binary system, the number of digits in the decimal system increase as, EQU . . . +r.sub.2 (100)+r.sub.1 (10)+r.sub.0 (1),
compared to the binary equivalent, EQU . . . +r.sub.2 (1100100)+r.sub.1 (1010)+r.sub.0 (1),
where the integers r.sub.1, r, r.sub.3, . . . r.sub.n must be converted to the binary system and multiplied. Similarly, decimal numbers less than 1 requires an increasing number of terms as the base integer decreases.
Increasing the radix of the number system sharply decreases the number of `gates` that must physically be formed on integrated circuit chips required for numeric expression. For example, the binary equivalent of the decimal number 1,000 is the unwieldy 1111101000, requiring 250% more `gates` to allow expression of the decimal equivalent. The binary number 100101101001 require 300% more gates than its decimal equivalent 2409. As number representations become much larger the gate equivalents become huge. Programmers try to alleviate the burden of working with binary `machine code` directly by resorting to binary shorthand codes like Octal and Hexadecimal, then converting back to binary.
This analysis of higher order number systems, showing radix higher than binary, predicts that a multi-state electronic device holds considerable applicability to meeting the goal of high performance, low power consumption, high circuit density, high manufacturing yield compared with conventional binary technologies.
Charge Transfer Devices
Charge-coupled devices (CCDS, or CTDS) are semiconductor systems in which charge packets are stored in potential wells created at the surface or within the bulk of a semiconductor and in which these charges are transferred by displacing the potential wells. The charges displaced in devices of the Surface CCD (SCCD) type are minority carriers of the semiconductor substrate, for example electrons if the semiconductor is of the p-type, or majority carriers in Bulk CCD (BCCD) devices. For background information on the general properties of these charge-coupled devices, reference can be made to the two original articles published on this subject in the "Bell System Technical Journal", volume 49. 1970 and entitled respectively "Charge-coupled semi-conductor devices" by W. S. Boyle and G. E. Smith (page 587) and "Experimental verification of the charge-coupled device concept" by G. F. Amelio, M. F. Tompsett and J. E. Smith (page 5933).
This charge transfer mechanism is accomplished by application of variable voltage to neighboring capacitors making it possible to transfer the charge packet because the charges accumulate where the voltage well is the deepest. This mechanism of adjoining MOS capacitors arranged to allow electronic charge transfer comprises, in very broad outline, a doped semiconductor substrate, a layer of insulating material, and an array of metallic electrodes which are brought to suitable potentials. The MOS electrodes are systematically arranged so that charge-packets can be transferred along the CCD register. Conventionally, SCCDs sequentially transfer the charge packet of minority carriers along a series of transfer electrodes in step with a square wavepulse of uniform amplitude.
A group of electrodes with a common electric link is called a phase. The command signals applied to the MOS electrodes are sequential and are called clocks. Each phase is driven by a distinct clock signal. All the clocks together form a clock timing sequence which must be carefully adjusted (to optimize elements such as the speed, the number of clock signals to be sent to the CCD, the relative phasing of the clocks, etc.) for each type of CCD. There are numerous transfer methods, specific fora given type of CCD, and they generally differ by the number of phases involved.
In the first charge-coupled devices, each of three clocks were connected by control lines to one electrode out of three. These were followed by a design of CCD having only two control lines in which asymmetrical potential wells are created beneath the electrodes. By way of example, reference can be made to U.S. Pat. No. 1,829.884 filed Jan. 13, 1972. and to the article by W. F. Kosonockv and J. E. Carmes published in the IEEE Journal of the Solid State Circuit, volume 6, No. 5, October, 1971 and entitled "Charge-coupled digital circuit". In these devices, the asymmetrical potential created beneath the electrodes is obtained either by means of surface region which is more heavily doped beneath the upstream edge of the electrode than beneath the remainder of the electrode or by means of different thickness of oxide from one edge of the electrode to the other. Charge-coupled devices have also been proposed in which only one control line is connected to all the electrodes. 1.O slashed., 2.O slashed., and 4.O slashed. state-of-the-art CCDs are alternative to the 3.O slashed. type described herein as illustrative of one embodiment of the present invention.
Depletion Well Control
The essential construction of the CCD is an array of closely spaced side-by-side MOS capacitors. By sequential application of electrode voltage, transfer of the minority carrier charge packet to succeeding electrodes is accomplished by the technology of depletion layers overlap. Thus formation of sequential overlapping depletion layers allows the charge packet to be stepped electrode to electrode.
The MOS structure is essentially an electrode very closely spaced from at semiconductor by a thin dielectric. For example, p-type silicon of about 10.sup.15 carrier density can be separated by a thin silicon dioxide layer about 0.1 .mu.m thick from an overlying aluminum electrode about 1 .mu.m thick. Application of increasing positive voltage to the electrode repels holes in the semiconductor under the electrode forming a depletion layer ranging from about 1-6 .mu.m deep until sufficient voltage causes an inversion layer of minority carrier's (electrons) to form immediately under the electrode. This inversion charge consists of approximately one million electrons for the MOS device parameters listed. Depletion layer deepening into the semiconductor shows a linear relationship with applied voltage to the gate. The depletion layer also occurs laterally from the electrode to almost the same distance as within the depth of the semiconductor. The equation describing the depth of the depletion layer is described physically by the equation, EQU .O slashed..sub.s =V.sub.G +V.sub.0 +Q.sub.INV /C.sub.OX -[2(V.sub.G+ Q.sub.INV /C.sub.OX)V.sub.0 +(V.sub.0).sup.2 ].sup.1/2,
where V.sub.0 is a constant given by (qN.sub.A.di-elect cons..sub.s) / (C.sub.OX).sup.2, q is electronic charge, N.sub.A is acceptor atom doping level, Q.sub.INV is the inversion layer charge, C.sub.OX i s the oxide capacitance, V.sub.G is the voltage applied to the gate, and .di-elect cons..sub.s is the permittivity of silicon. A good approximation for .O slashed..sub.s is the linear expression,
.O slashed..sub.s =V.sub.G +Q.sub.INV /C.sub.OX
because of the lightly doped substrates and thin oxides usually used for CCD structures. (V.sub.0 is about 0.14, for a 0.1 .mu.m oxide, for example, compared to many volts for V.sub.G).
There are a number of state-of-the-art methods to fix the specific gate voltage, V.sub.G, necessary to allow charge transfer from one electrode to the next. One method is to control the physical distance of MOS capacitor electrode A (i.e., the `source`) from electrode B (i.e., the `drain`). A wider spacing requires higher electrode voltage to allow the depletion layer to spread to the next adjacent electrode and thereby allow transfer of the inversion charge packet. Gate dielectric thickness control is another. Another way is by means of ion implantation.
Ion Implantation
One particularly useful way to control the electrode voltage necessary for charge transfer is by ion implantation, an IC process now well established. This is usually accomplished by either controlling charge in the gate dielectric or by implantation of ions in the semiconductor immediately between the electrodes. This control of dopant density in the semiconductor between the `source` and `drain` is the preferred way to accomplish stable threshold control because semiconductor dopant density can be set very exactly by use of ion implantation.
Ion implantation is an IC process now so well controlled that it is widely used in the microelectronics industry to achieve precise desired threshold voltage in CMOS devices, for channel stop implantation, source/drain formation, graded source and drains, and in particular for precision control of charge well formation. Ion implantation is a physical process not a chemical process like diffusion. The process takes place at room temperature and there is no side diffusion due to high temperature processing. Consequently, there is greater control of doping concentrations. The following are the important advantages of ion implantation: (a) precise control of implanted dopant atoms into photolithographically defined areas of a substrate to within 1.5% for dopant control in the 10.sup.14 to 10.sup.18 atoms/cm.sup.3 range, (b) less lateral distribution of implanted impurities compared to diffusion processes (thus allowing smaller feature dimensions). (c) dopant injection through thin oxide layers allowing precision control of MOS threshold voltage while the SiO acts as a protective screen to other contaminants, (d) predicted ranges of implanted ions fits experimental data very well, high energy light ions within 2%, (e) highly abrupt junctions can be formed, (f) uniform doping across large wafers can be achieved, (g) photoresist can be used as a mask.
By the ion implantation process, energetic charged atoms or molecules of a particular species can be implanted in a semiconductor to the exact quantity required. By this method charge transfer threshold voltage can be closely controlled by adjustment of the substrate doping, P. under and/or between the required MOS transfer electrode. The equation describing this relationship is, EQU V.sub.G -V.sub.FB =V.sub.s +I/C.sub.OX (2K.sub.S e.sub.0 qN.sub.A V.sub.S).sup.1/2
The dopant density N affects the surface potential, consequently the gate voltage required to produce inversion. Since dopant density at the surface of the semiconductor can very accurately be set in a MOS gate by ion implantation, consequently the voltage required to allow charge transfer in a CCD can be accurately set. Threshold voltage in NMOS gate transfer regions of a CCD device can be controlled, for example, by implanting a precise quantity of Boron atoms through the thin gate oxide of an NMOS CCD charge transfer region to adjust transfer voltage. V.sub.T changes by EQU .DELTA.V.sub.T =-.DELTA.Q.sub.B /C.sub.OX
where .DELTA.Q.sub.B is the change of the sheet ionized dopant charge in the channel, and C.sub.OX is the gate oxide capacitance per unit area. By selecting a suitable energy, the B atoms just penetrate the thin oxide (.about.200-500 .ANG.) of the device regions, but not the thicker oxide (.about.7500 .ANG.) of the field regions. The projected ranges of B in Si and SiO2 are about the same, making the correct selection of the implantation energy a relatively simple task.
Photoresist and thin metal layers can be used as doping barriers along with thin silicon dioxide layers. Localization of the charge can be controlled using photolithographic means whereby resist is left in areas where implant is not desired. In fact the implanted species can be controlled so as to be located at a particular desired depth in the semiconductor. Ion implantation technology holds the most promise for a reliable and reproducible multi-state electronic component, the subject of the invention herein.